Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs
复制标题
包含查找表和 PLA 的混合 FPGA 的技术映射算法
DOI：
10.1109/tcad.2003.810743
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
R. Tessier
中科院分区：
文献类型：
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作者：
Srini Krishnamoorthy;R. Tessier
包含查找表（LUT）和可编程逻辑阵列（PLA）的可编程器件为用户设计提供了异构目标平台。目前的商业工具，其目标是这些混合设备，需要手动分区的用户设计，以隔离每种类型的逻辑资源的逻辑。在本文中，一个自动化的技术映射工具，hybridmap，提出了识别设计逻辑分区适合于LUT或PLA实现。一个基于广度优先搜索的子图提取和评估启发式集成产品术语（Pterm）计数，面积和延迟估计，以指导技术映射过程。Hybridmap可以适应各种PLA架构，并可以适应用户提供的时间约束。结果表明，当时序约束，hybridmap减少查找表消耗的Apex20KE设备的8%，当不受约束的14%，通过迁移逻辑从LUT到Pterm结构。Hybridmap的性能比Apex20KE型设备的先前映射方法高出22%。
Programmable devices containing lookup tables (LUTs) and programmable logic arrays (PLAs) provide a heterogeneous target platform for user designs. Present commercial tools, which target these hybrid devices, require hand partitioning of user designs to isolate logic for each type of logic resource. In this paper, an automated technology mapping tool, hybridmap , is presented that identifies design logic partitions as suitable for either LUT or PLA implementation. A breadth-first search-based subgraph extraction and evaluation heuristic is integrated with product term (Pterm) count, area, and delay estimators to guide the technology mapping process. Hybridmap can be adapted to target a variety of PLA architectures and can accommodate user-provided timing constraints. It is shown that when timing constrained, hybridmap reduces LUT consumption for Apex20KE devices by 8% and when unconstrained by 14% by migrating logic from LUTs to Pterm structures. Hybridmap is shown to outperform previous mapping approaches for Apex20KE-type devices by up to 22%.