A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs
A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs
复制标题
一种位交错嵌入式汉明方案，用于纠正基于 SRAM 的 FPGA 的单位和多位翻转
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Akash Kumar
中科院分区：
文献类型：
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作者：
Shyamsundar Venkataraman;Rui Santos;Anup Das;Akash Kumar
单个事件UPSETS（SEUS）无意间更改了基于静态RAM（SRAM）的字段可编程门阵列（FPGA）的配置位，导致错误输出直到纠正错误。使用误差校正代码（ECC）（例如锤）进行擦洗是纠正此类故障的一种流行方法。但是，当前的作品要么需要大的外部内存来存储ECC，要么最多才能在框架中只能正确一个错误。本文提出了一种新型的刻度嵌入式锤子方案以及擦洗，以纠正基于SRAM的FPGA中的单个（SBU）和多位倒入（MBU）。该方案不需要外部内存来存储ECC，因为它们嵌入了配置内存本身中。通过各种基准进行的实验表明，所提出的方案可以很好地处理每个框架的多个错误，其嵌入效率超过99.3％。
Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Scrubbing using an Error Correction Code (ECC) such as hamming is a popular method to correct such faults. However, current works either require a large external memory to store the ECCs or can at most correct only one error in a frame. This paper proposes a novel bit-interleaved embedded hamming scheme along with scrubbing, to correct single (SBUs) and multi-bit upsets (MBUs) in SRAM-based FPGAs. This scheme does not require an external memory to store the ECCs, as they are embedded within the configuration memory itself. Experiments conducted on various benchmarks show that the proposed scheme can handle multiple errors per frame very well, with an embedding efficiency of over 99.3%.