3D clock distribution using vertically/horizontally-coupled resonators
3D clock distribution using vertically/horizontally-coupled resonators
复制标题
使用垂直/水平耦合谐振器的 3D 时钟分配
DOI：
10.1109/isscc.2013.6487725
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
T. Kuroda
中科院分区：
文献类型：
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作者：
Yasuhiro Take;N. Miura;H. Ishikuro;T. Kuroda
对于高性能微处理器来说，低偏移、低抖动和低功耗的时钟分配是一个重大的设计挑战。虽然传统的H树时钟分配电路被广泛使用，但这种电路的时钟偏斜会因与器件缩放相关的PVT变化而增加[1]。因此，近年来，对于用于减小时钟偏斜的谐振时钟分配方案的兴趣日益增长。特别是，与LC谐振器[3]相比，具有短路输出的耦合环形振荡器[2]可以减少偏斜和抖动，而无需额外的布局面积。每个振荡器的相位和频率的差异（由于PVT变化）通过振荡器之间的相互连接来均衡。功率耗散也可以减少，因为增强的可变性容限可以允许在较低电压下操作。
Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.