IP Core Identification in FPGA Configuration Files using Machine Learning Techniques
IP Core Identification in FPGA Configuration Files using Machine Learning Techniques
复制标题
使用机器学习技术识别 FPGA 配置文件中的 IP 核
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
D. Göhringer
中科院分区：
文献类型：
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作者：
Safdar Mahmood;J. Rettkowski;Arij Shallufa;M. Hübner;D. Göhringer
在现代工业和科学研究中，关于实验场景、真实的世界应用或消费电子产品，现场可编程门阵列（FPGA）正成为流行的选择。FPGA非常独特的性质使相关嵌入式设计具有可重构性，可扩展性和自适应性，使其成为传统硬件的显着替代品。FPGA能够在运行时通过卸载和加载位流的方式完全或部分地动态重新配置自身。本文介绍了一种利用有监督机器学习对FPGA码流进行分析和检测的方法。通过利用机器学习，我们演示了如何训练神经网络来识别和跟踪FPGA位流中具有某些已知功能的特定硬件模块或IP核（知识产权核）。我们通过结合人工神经网络（ANN）进行FPGA比特流的分析，分类范围从多层感知器（MLP）或现代卷积神经网络（CNN）。
In modern day industry and scientific research, pertaining to experimental scenarios, real world applications or consumer electronics, Field Programmable Gate Arrays (FPGAs) are becoming a popular choice. The very distinctive nature of FPGAs enables reconfigurability, scalability and adaptivity of the associated embedded design which makes it a remarkable alternative to traditional hardware. An FPGA is able to dynamically reconfigure itself during run-time, entirely or partially, by way of unloading and loading bitstreams. In this paper, an approach is introduced to analyze and inspect FPGA bitstreams by making use of supervised machine learning. By exploiting machine learning, we demonstrate how neural networks can be trained to identify and trace a certain hardware module or an IP core (Intellectual Property core) with some known functionality in FPGA bitstreams. We perform an analysis of FPGA bitstreams by incorporating Artificial Neural Networks (ANNs) based classification ranging from Multiple Layer Perceptrons (MLPs) or to modern Convolutional Neural Networks (CNNs).