PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations
PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations
复制标题
PPAC：用于类似矩阵向量乘积运算的多功能内存加速器
DOI：
--
复制
发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Christoph Studer
中科院分区：
文献类型：
--
作者：
Oscar Castañeda;Maria Bobbett;Alexandra Gallyas;Christoph Studer
内存处理（PIM）将计算转移到内存中，与传统的基于冯·诺伊曼的架构相比，目标是提高吞吐量和能源效率。大多数现有的PIM体系结构要么是通用的，但只支持原子操作，要么专门用于加速单个任务。我们提出了关联内容可寻址存储器（PPAC）中的并行处理器，这是一种新型的内存加速器，支持一系列类似矩阵向量积（MVP）的操作，这些操作在传统和新兴应用中都有使用。例如，PPAC能够加速低精度神经网络、精确/近似哈希查找、加密和前向纠错。PPAC的全数字化特性使其能够与基于标准单元的CMOS一起实现，从而促进了技术节点之间的自动化设计和可移植性。为了证明PPAC的有效性，我们在28nm CMOS上提供了不同阵列尺寸的布局后实现结果。与最近的数字和混合信号PIM加速器的比较表明，PPAC在吞吐量和能效方面具有竞争力，同时加速了广泛的应用并简化了开发。
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. We propose the Parallel Processor in Associative Content-addressable memory (PPAC), a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cell-based CMOS, which facilitates automated design and portability among technology nodes. To demonstrate the efficacy of PPAC, we provide post-layout implementation results in 28nm CMOS for different array sizes. A comparison with recent digital and mixed-signal PIM accelerators reveals that PPAC is competitive in terms of throughput and energy-efficiency, while accelerating a wide range of applications and simplifying development.