Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing
Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing
复制标题
用于近似计算的无源开关电容矩阵乘法器的分析与设计
DOI：
10.1109/jssc.2016.2599536
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发表时间：
2016
影响因子：
5.4
通讯作者：
S. Wong
中科院分区：
文献类型：
--
作者：
Edward A. Lee;S. Wong
提出了一种开关电容矩阵乘法器，用于近似计算和机器学习。乘法和累加操作使用无源开关和300 aF单位电容器执行离散时间电荷域信号处理。计算采用6 B异步逐次逼近寄存器模数转换器进行数字化。讨论了不完全电荷积累和热噪声的分析。该设计是在40 nm CMOS制造的，乘法的实验测量说明使用匹配滤波和图像卷积来分析噪声和偏移。突出显示了两个应用：1）在用于模拟前端的神经网络中执行压缩和分类的节能特征提取层，以及2）用于解决传统上在数字域中执行的优化问题的模拟加速。该芯片在第一次应用中获得了8.7 TOPS/W的测量效率，在2.5 GHz时获得了7.7 TOPS/W的测量效率。
A switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications. The multiply-and-accumulate operations perform discrete-time charge-domain signal processing using passive switches and 300 aF unit capacitors. The computation is digitized with a 6 b asynchronous successive approximation register analog-to-digital converter. The analyses of incomplete charge accumulation and thermal noise are discussed. The design was fabricated in 40 nm CMOS, and experimental measurements of multiplication are illustrated using matched filtering and image convolutions to analyze noise and offset. Two applications are highlighted: 1) energy-efficient feature extraction layer performing both compression and classification in a neural network for an analog front end and 2) analog acceleration for solving optimization problems that are traditionally performed in the digital domain. The chip obtains measured efficiencies of 8.7 TOPS/W at 1 GHz for the first application and 7.7 TOPS/W at 2.5 GHz for the second application.