Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge
Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge
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DOI:
10.1109/mm.2022.3195761
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发表时间:
2022-11
期刊:
影响因子:
3.6
通讯作者:
S. Ollivier;Xinyi Zhang;Yue Tang;C. Choudhuri;Jingtong Hu;A.K. Jones
中科院分区:
文献类型:
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作者:
S. Ollivier;Xinyi Zhang;Yue Tang;C. Choudhuri;Jingtong Hu;A.K. Jones
Convolutional neural networks (CNNs) have become a ubiquitous algorithm with growing applications in mobile and edge settings. We describe a compute-in-memory (CIM) technique called POD-RACING using Racetrack memory (RM) to accelerate CNNs for edge systems. Using transverse read, a technique that can determine the number of “1”s in multiple adjacent domains, POD-RACING can efficiently implement multioperand bulk-bitwise and addition computations, and two-operand multiplication. We discuss how POD-RACING can implement both variable precision integer and floating point arithmetic using digital CIM. This allows both CNN inference and on-device training without expensive data movement to the cloud. Based on these functions we demonstrate the implementation of several CNNs with backpropagation using RM CIM and compare these to the state-of-the-art implementations of CNN inference and training. During training, POD-RACING improves efficiency by 2×, energy consumption by $\geq$≥27%, and increases throughput by $\geq$≥18% versus a state-of-the-art field-programmable gate array accelerator.