Architectural Considerations in the Design of a Superconducting Quantum Annealing Processor
Architectural Considerations in the Design of a Superconducting Quantum Annealing Processor
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DOI：
10.1109/tasc.2014.2318294
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发表时间：
2014-08-01
影响因子：
1.8
通讯作者：
Whittaker, Jed
中科院分区：
文献类型：
--
作者：
Bunyk, Paul I.;Hoskinson, Emile M.;Whittaker, Jed
我们已经开发了一个量子退火处理器，基于一个可调耦合rf-SQUID通量量子比特阵列，在超导集成电路工艺制造。以512个量子位和1472个可编程量子位间耦合器的规模实现这种类型的处理器，并以类似于20 mK的速度运行，需要注意许多考虑因素，这些考虑因素在几十个左右的较小规模设备中可能会被忽略。在这里，我们将讨论其中的一些考虑因素，以及构建一个实用处理器所需的微妙平衡，该处理器尊重量子算法所施加的苛刻物理要求。特别是，我们将审查一些在物理布局的平面规划中起作用的设计权衡，由具有一组在算法上有用的量子位间耦合器的愿望驱动，同时需要将可编程控制电路嵌入到处理器结构中。在这种情况下，我们已经开发出一种新的超低功耗嵌入式超导数模磁通转换器（DAC）用于编程处理器的零静态功耗，优化，以实现最大的磁通存储密度每单位面积。512个单级、3520个两级和512个三级通量DAC采用XYZ寻址方案控制，需要56根导线。我们对整个处理器在最坏情况下重新编程的片内耗散能量的估计与65 fJ相似。基于这种架构的几个芯片已经在我们的工厂和两个外部工厂成功制造和运行（例如，参见Jones最近的报告）。
We have developed a quantum annealing processor, based on an array of tunable coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process. Implementing this type of processor at a scale of 512 qubits and 1472 programmable interqubit couplers and operating at similar to 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here, we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular, we will review some of the design tradeoffs at play in the floor planning of the physical layout, driven by the desire to have an algorithmically useful set of interqubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context, we have developed a new ultralow-power embedded superconducting digital-to-analog flux converter (DAC) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is similar to 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see, for example, the recent reporting by Jones).