Addressing Cu/Low-$k$ Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies
Addressing Cu/Low-$k$ Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies
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DOI：
10.1109/ted.2008.2008680
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发表时间：
2009
影响因子：
3.1
通讯作者：
Fen Chen;M. Shinosky
中科院分区：
文献类型：
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作者：
Fen Chen;M. Shinosky
低介电常数晶体对于改善芯片阻容延迟、减小串扰噪声和降低功耗是先进超大规模集成电路，特别是高性能逻辑电路的持续扩展所不可缺少的。在本文中，几个关键的挑战，铜/低k的时间相关的介质击穿（TDDB）的可靠性鉴定将进行审查。首先，将讨论低k TDDB场加速模型及其确定。其次，宏观互连线间距的变化在整个晶圆和微观线间距的不均匀性引起的线边缘粗糙度在同一测试结构和它们的影响低k TDDB可靠性将仔细检查。威布尔形状参数依赖于所施加的应力电压，由于这种全球和局部的间距变化将进行分析。最后，水分对低k TDDB和电容稳定性的影响作为一个例子，从工艺集成的影响将被报告，表明低k TDDB是敏感的后端的线集成。
Low-k dielectrics, which are beneficial for chip resistance-capacitance (RC) delay improvement, crosstalk-noise minimization, and power-dissipation reduction, are indispensable for the continuous scaling of advanced VLSI circuits, particularly that of high-performance logic circuits. In this paper, several critical challenges for Cu/low-k time-dependent dielectric-breakdown (TDDB)-reliability qualification will be reviewed. First, a low-k TDDB field-acceleration model and its determination will be discussed. Second, the macroscopic interconnect line-to-line spacing variation across the wafer and the microscopic line-to-line spacing nonuniformity induced by line-edge roughness within the same test structure and their impacts on low- k TDDB reliability will be carefully examined. The Weibull shape-parameter dependence on applied stress voltage due to such global and local spacing variations will be analyzed. Finally, the moisture effect on low-k TDDB and capacitance stability as an example of the impact from process integration will be reported, demonstrating that low-k TDDB is sensitive to back-end-of-the-line integration.