Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule
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DOI：
10.1093/ietfec/e89-a.4.969
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发表时间：
2006-04
期刊：
影响因子：
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通讯作者：
K. Shimizu;T. Ishikawa;N. Togawa;Takeshi Ikenaga;Satoshi Goto
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文献类型：
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作者：
K. Shimizu;T. Ishikawa;N. Togawa;Takeshi Ikenaga;Satoshi Goto
本文提出了一种部分并行的LDPC译码方案，实现了一种高效的消息传递调度。所提出的LDPC译码器的特点如下：(I)在流水线结构中，列操作遵循行操作，以确保行操作和列操作同时执行。(Ii)提出的并行流水线比特功能单元使列运算模块能够计算在行运算更新的每个比特节点中的每条消息。当同时执行行和列操作时，可以在不延长单个迭代解码延迟的情况下执行这些列操作。因此，所提出的解码器在单次迭代译码中执行列操作的频率更高，并且在有限的译码延迟时间内实现了高效的消息传递调度。硬件实现和仿真结果表明，提出的部分并行LDPC译码器在较小的硬件开销下提高了译码吞吐量和误码性能。
In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.