Hardware-assisted power estimation for design-stage processors using FPGA emulation
Hardware-assisted power estimation for design-stage processors using FPGA emulation
复制标题
使用 FPGA 仿真对设计阶段处理器进行硬件辅助功耗估算
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
H. Blume
中科院分区：
文献类型：
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作者：
Sebastian Hesselbarth;Tim Baumgart;H. Blume
本文提出了一个精确的功耗估计模型的设计阶段的处理器，可以映射到FPGA上的功能仿真的应用。基于混合功能级功耗分析（FLPA）和指令级功耗分析（ILPA）的方法，该模型能够在可编程嵌入式处理器的早期设计阶段估计特定于应用的功耗和每个任务的能量。与门传输级（GTL）功耗仿真相比，仿真功耗模型的执行时间极短，这使得硬件和软件设计人员能够在不同的设计阶段不断优化其低功耗实现。用于这项工作的功耗建模方法和FPGA实现的必要考虑进行了说明。所提出的模型进行了验证，对GTL功率仿真的执行时间和精度的基准为一个示例性的嵌入式RISC处理器内核，LEON 2。基准测试结果产生小于9%的百分比平均绝对误差（%MAE）和小于6%的归一化均方根误差（NRMSE），同时将功率估计时间从几个小时减少到几毫秒。最后，不同的真实世界的输入数据大小的案例研究已经进行了不同的软件实现的JPEG编码器和解码器的应用程序和优化的处理器内核。通过软件和硬件优化，JPEG编码器和JPEG解码器的每项任务所需能量分别降低了46%和39%，证明了所提出方法的优势。
This paper presents the application of an accurate power estimation model for design-stage processors that can be mapped onto an FPGA together with the functional emulation. Based on a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach, the model enables the estimation of application-specific power consumption and energy per task at very early design stages of programmable embedded processors. The extremely short execution time of the emulated power model compared to gate-transfer level (GTL) power simulation allows both hardware and software designers to constantly optimize their implementations for low-power iteratively in different design stages. The power consumption modeling methodology used for this work and necessary considerations for FPGA implementation are described. The presented model is validated against GTL power simulation with respect to execution time and precision by benchmarking for an exemplary embedded RISC processor core, the LEON2. Benchmarking results yield a percentage mean absolute error (%MAE) of less than 9% and normalized root mean square error (NRMSE) of less than 6% while reducing power estimation time from several hours down to a few milliseconds. Finally, a case-study with varying real-world input data sizes has been performed on different software implementations of JPEG encoder and decoder applications and optimized processor core. With software and hardware optimizations applied, required energy per task has been reduced by up to 46% for the JPEG encoder and 39% for the JPEG decoder, demonstrating the advantage of the presented approach.