Symbol-Decision Successive Cancellation List Decoder for Polar Codes

Symbol-Decision Successive Cancellation List Decoder for Polar Codes
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DOI:
10.1109/tsp.2015.2486750
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发表时间:
2015-01
影响因子:
5.4
通讯作者:
Chenrong Xiong;Jun Lin;Zhiyuan Yan
Chenrong Xiong;Jun Lin;Zhiyuan Yan
中科院分区:
工程技术1区
文献类型:
--
作者:
Chenrong Xiong;Jun Lin;Zhiyuan Yan

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极性代码具有极大的兴趣,因为它们可以正确地实现具有任意输入字母大小的无内存通道的对称能力,同时具有显式构造。我们建议对符号决定成功取消(SC)和成功取消列表(SCL)对极性代码的解码器,这些解码器使用符号硬性或软决策首先,我们建议使用递归通道的组合来计算符号通道过渡的可能性,这会导致符号的决定,而不是简单地结合位宽道通道过渡的可能性,这是符号通道的过渡可能性。我们提出的方法与Arıkan的渠道转换之间的相似性也有助于分享计算位和计算位置的硬件资源符号频道过渡的可能性。 ,我们提出了一种预付内记忆的技术,以减少SCL解码器的内存需求。在该体系结构中的半平行取消列表解码器中,考虑了不同的符号,分类实现和消息调度方案。和多位SCL解码器。
Polar codes are of great interests because they provably achieve the symmetric capacity of discrete memoryless channels with arbitrary input alphabet sizes while having an explicit construction. Most existing decoding algorithms of polar codes are based on bit-wise hard or soft decisions. In this paper, we propose symbol-decision successive cancellation (SC) and successive cancellation list (SCL) decoders for polar codes, which use symbol-wise hard or soft decisions for higher throughput or better error performance. First, we propose to use a recursive channel combination to calculate symbol-wise channel transition probabilities, which lead to symbol decisions. Our proposed recursive channel combination has lower complexity than simply combining bit-wise channel transition probabilities. The similarity between our proposed method and Arıkan's channel transformations also helps to share hardware resources between calculating bit- and symbol-wise channel transition probabilities. Second, a two-stage list pruning network is proposed to provide a trade-off between the error performance and the complexity of the symbol-decision SCL decoder. Third, since memory is a significant part of SCL decoders, we propose a pre-computation memory-saving technique to reduce memory requirement of an SCL decoder. Finally, to evaluate the throughput advantage of our symbol-decision decoders, we design an architecture based on a semi-parallel successive cancellation list decoder. In this architecture, different symbol sizes, sorting implementations, and message scheduling schemes are considered. Our synthesis results show that in terms of area efficiency, our symbol-decision SCL decoders outperform existing bit-decision and multi-bit SCL decoders.