A Novel Transmission-Line Deembedding Technique for RF Device Characterization
A Novel Transmission-Line Deembedding Technique for RF Device Characterization
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DOI：
10.1109/ted.2009.2032608
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发表时间：
2009-11
影响因子：
3.1
通讯作者：
Hsiu-Ying Cho;Jiun-Kai Huang;C. Kuo;Sally Liu;Chung-Yu Wu
中科院分区：
文献类型：
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作者：
Hsiu-Ying Cho;Jiun-Kai Huang;C. Kuo;Sally Liu;Chung-Yu Wu
提出了一种新的传输线去嵌入技术。利用该技术，可以使用长度为L和2L的两个传输线测试结构直接提取左侧和右侧接地-信号-接地探针焊盘。在现有的去嵌入方法中，采用过孔堆栈去嵌入的方法设计了一个额外的直通结构。所提出的方法的优点包括：1）更小的硅面积; 2）焊盘和互连之间的不连续性; 3）衬底耦合和接触效应;以及4）使用过孔堆叠去嵌入。所提出的新方法是超高频去嵌入领域的重大突破，应该能够开发出更准确的RF模型。在所提出的方法中，本征慢波CPW传输线结构被放置在层间金属化层上，因为它们是最合适的RF器件，用于涉及通孔堆叠去嵌入技术的基于级联的去嵌入方法。实验结果表明，通过改变金属密度和金属层在浮动屏蔽上的位置，可以优化衰减损耗和波长。测量和电磁波模拟进行了高达50 GHz。在缩短波长的情况下，通过使用优化的槽型浮动屏蔽，可以实现超过66%的硅面积减少。
A novel transmission-line deembedding technique is presented in this paper. With this technique, the left- and right-side ground-signal-ground probe pads can be extracted directly using two transmission-line test structures of length L and 2L. An additional through structure is designed using via-stack deembedding, which is unique among current deembedding methods. The advantages of the proposed method include the following: 1) smaller silicon area; 2) discontinuity between the pad and interconnect; 3) substrate coupling and contact effects; and 4) employment of via-stack deembedding. The proposed novel methodology is a great breakthrough in the area of ultrahigh-frequency deembedding and should enable more accurate RF models to be developed. In the proposed methodology, intrinsic slow-wave CPW transmission-line structures are placed on the interlevel metallization layers, as they are the most appropriate RF device for cascade-based deembedding method involving the via-stack deembedding technique. Experimental results have demonstrated that attenuation loss and wavelength can be optimized by changing the metal density and the position of the metal layer on the floating shields. Both measurement and electromagnetic-wave simulations were performed up to 50 GHz. With a shortened wavelength, a reduction in silicon area of more than 66% can be achieved by using optimized slot-type floating shields.