Toward systematic architectural design of near-term trapped ion quantum computers
Toward systematic architectural design of near-term trapped ion quantum computers
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DOI：
10.1145/3511064
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发表时间：
2022-02
影响因子：
22.7
通讯作者：
Prakash Murali;D. Debroy;K. Brown;M. Martonosi
中科院分区：
文献类型：
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作者：
Prakash Murali;D. Debroy;K. Brown;M. Martonosi
捕获离子（TI）是构建噪声中尺度量子（NISQ）硬件的主要候选者。TI量子比特比其他技术具有根本优势，具有高量子比特质量，相干时间和量子比特连接性。然而，当前的TI系统尺寸小，并且通常使用单个陷阱架构，这具有基本的可扩展性限制。为了朝着50- 100量子位TI器件的下一个重要里程碑前进，已经提出了一种称为量子电荷耦合器件（QCCD）的模块化架构。在基于QCCD的TI设备中，小阱通过离子穿梭连接。虽然已经展示了这种设备的基本硬件组件，但构建50- 100量子位系统是具有挑战性的，因为陷阱大小，通信拓扑和门实现的设计可能性很大，并且需要匹配不同的应用资源要求。为了实现具有50- 100量子位的基于QCCD的TI系统，我们进行了广泛的应用驱动的体系结构研究，评估了陷阱尺寸、通信拓扑和操作实现方法的关键设计选择。为了使我们的研究，我们建立了一个设计工具流，它需要一个QCCD架构的参数作为输入，沿着一组应用程序和现实的硬件性能模型。我们的工具流将应用程序映射到目标设备上，并模拟它们的执行，以计算应用程序运行时间、可靠性和设备噪声率等指标。使用六个应用程序和几个硬件设计点，我们表明，陷阱大小和通信拓扑结构的选择可以影响应用程序的可靠性高达三个数量级。微架构门实现的选择影响可靠性的另一个数量级。通过这些研究，我们提供了具体的建议来调整这些选择，以实现高度可靠和高性能的应用程序执行。随着行业和学术界正在努力构建具有50-100量子位的TI设备，我们的见解有可能在不久的将来影响QC硬件，并加速实用QC系统的进展。
Trapped ions (TIs) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies, featuring high qubit quality, coherence time, and qubit connectivity. However, current TI systems are small in size and typically use a single trap architecture, which has fundamental scalability limitations. To progress toward the next major milestone of 50--100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50--100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology, and gate implementations and the need to match diverse application resource requirements. Toward realizing QCCD-based TI systems with 50--100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology, and operation implementation methods. To enable our study, we built a design toolflow, which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability, and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near future and accelerate the progress toward practical QC systems.