Phase difference analysis technique for parametric faults BIST in CMOS analog circuits
Phase difference analysis technique for parametric faults BIST in CMOS analog circuits
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DOI：
10.1587/elex.15.20180175
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发表时间：
2018-04
期刊：
影响因子：
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通讯作者：
C. Wannaboon;N. Jiteurtragool;W. San-Um;M. Tachibana
中科院分区：
文献类型：
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作者：
C. Wannaboon;N. Jiteurtragool;W. San-Um;M. Tachibana
：由于制造工艺的巨大变化，参数故障的检测是一个至关重要的问题，这在模拟电路中提供了一系列可接受的参数偏差。本文提出了一种相位差分析技术，该技术对参数偏差很敏感，并且允许无源模拟元件的公差带。通过比较参考时钟信号和重新配置的被测电路（CUT）作为振荡器之间的相位差，可以简单地实现测试操作。两个信号之间的相位特性差异可以用作故障特征的指示符，其可以通过包括计数器和逻辑组件的紧凑数字电路来表征。故障检测仿真揭示了高故障覆盖率、高速测试和公差带可控性。所提出的技术提供了采用 0.18 µm CMOS 标准技术的完全片上 BIST，无需外部测试设备。
: Detection of parametric faults is a crucial issue due to the large variation of the fabrication process, which provide a range of acceptable parameter deviations in analog circuits. This paper presents a phase di ff er-ence analysis technique, which is sensitive to the parametric deviations and allows a tolerance band of passive analog components. Test operations can be simply achieved by comparing the phase di ff erence between a reference clock signal and a recon fi gured circuit-under-test (CUT) as an oscillator. The di ff erence of phase characteristics between the two signals can be utilized as an indicator for a fault signature, which can be characterized by a compact digital circuit comprising a counter and logic components. Simulation of faults detection reveals a high faults coverage, high-speed testing, and tolerance band controllability. The proposed technique has o ff ered a fully on-chip BIST in 0.18-µm CMOS standard technology with no external test equipment required.