NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures
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DOI：
10.1109/access.2019.2942129
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发表时间：
2019-09
期刊：
影响因子：
3.9
通讯作者：
J. Joseph;Lennart Bamberg;Dominik Ermel;Behnam Razi Perjikolaei;Anna Drewes;Alberto García-Ortiz;Thilo Pionteck
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文献类型：
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作者：
J. Joseph;Lennart Bamberg;Dominik Ermel;Behnam Razi Perjikolaei;Anna Drewes;Alberto García-Ortiz;Thilo Pionteck
异源3D系统（3D SOC）是将传感和计算在单个芯片中结合的最有前途的设计范式这项工作，这种差异大大降低了网络性能。局限性。我们分析了异质性的挑战：技术意识模型用于通信，从而确定数据包的传播较慢。从90到28m的各种商业技术的时间误差小于7.4％。提出两种称为Z+（XY）Z-和ZXYZ的新型路由算法，与传统的尺寸订单相比，将延迟提高到$ 6.5 \ times $。这完全克服了较慢的层，我们与传统的路由器相比，将吞吐量增加了2至4美元。减少了41.1％，我们在实际路由器面积的小额面积和申请情况下，以较小的总路由器面积成本在2.1％至10.4％的情况下，Flit Latenty thimes $ $ 2.26 \ times $ $。
Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication networks in heterogeneous 3D SoCs is the varying latency and throughput in each layer. As shown in this work, this variance drastically degrades the network performance. We contribute a co-design of routing algorithms and router microarchitecture that allows to overcome these performance limitations. We analyze the challenges of heterogeneity: Technology-aware models are proposed for communication and thereby identify layers in which packets are transmitted slower. The communication models are precise for latency and throughput under zero load. The technology model has an area error and a timing error of less than 7.4% for various commercial technologies from 90 to 28nm. Second, we demonstrate how to overcome limitations of heterogeneity by proposing two novel routing algorithms called Z+(XY)Z− and ZXYZ that enhance latency by up to $6.5\times $ compared to conventional dimension order routing. Furthermore, we propose a high vertical-throughput router microarchitecture that is adjusted to the routing algorithms and that fully overcomes the limitations of slower layers. We achieve an increased throughput of 2 to $4\times $ compared to a conventional router. Thereby, the dynamic power of routers is reduced by up to 41.1% and we achieve improved flit latency of up to $2.26\times $ at small total router area costs between 2.1% and 10.4% for realistic technologies and application scenarios.