Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"
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基于集成平台“UniPhier”的移动应用SoC低功耗技术
DOI：
10.1109/aspdac.2007.358060
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
M. Sumita
中科院分区：
文献类型：
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作者：
M. Nakajima;Takao Yamamoto;M. Yamasaki;T. Hosoki;M. Sumita
在本文中，我们描述了基于集成平台“UniPhier”的移动应用SoC的各种低功耗技术。为了最大限度地减少SoC功耗，采用了UniPhier Soc级、UniPhier处理器级、IPP（指令并行处理器）级和电路级的分层方法。作为 SoC 级别，1）UniPhier SoC 架构的 5 个主要单元功能隔离良好，2）专用流 DMA 控制器，可以最大限度地减少 CPU 负载和内存访问。作为UniPhier处理器级别，1）UniPhier处理器由具有专用低功耗硬件引擎的IPP组成，2）具有微睡眠的VMP（虚拟多处理器）机制，可以在多任务并发操作的情况下降低平均功耗，3）在非常轻负载操作的情况下，结合微睡眠和时钟/断电方案的间歇操作。作为IPP级别，1）复杂的取指令缓冲机制，可以减少50%以上的取指令内存访问。 2) 通过详细的时钟功率分析和实际应用的时钟活动率分析来实现分层和选择性时钟门控方案。) 通过低功耗库和选择性使用自定义宏来优化物理实现。在电路层面，采用固定Id和固定Vt控制的混合体偏置技术，与无体偏置相比，可以实现85％的延迟变化抑制和25％的ED产品改进。
In this paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, hierarchical approaches from UniPhier Soc level, UniPhier processor level, IPP (instruction parallel processor) level, and circuit level are adopted. As SoC level, 1) well functionally isolated 5 major units of UniPhier SoC architecture, 2) dedicated stream DMA controller which can minimize CPU load and memory access. As UniPhier processor level, 1) UniPhier processor consists of IPP with dedicated low power hardware engine, 2) VMP (virtual multi-processor) mechanism with micro sleep which can reduce average power consumption in case of multiple tasks concurrent operation, 3) intermittent operation with the combination of micro-sleep and clock/power down scheme in case of very light load operation. As IPP level, 1) sophisticated instruction fetch buffer mechanism which can reduce more than 50% memory access for instruction fetch. 2) Hierarchical and selective clock gating scheme by detailed clock power analysis and clock activity rate analysis on real application.) Optimized physical implementation with low-power library and selective use of custom macros. As circuit level, mixed body bias technique with fixed Id and fixed Vt control which can realize 85 % delay variation suppressed and 25% ED product improvement compared with the no body bias.