Characterizing Power Distribution Attacks in Multi-User FPGA Environments
Characterizing Power Distribution Attacks in Multi-User FPGA Environments
复制标题
表征多用户 FPGA 环境中的配电攻击
DOI：
10.1109/fpl.2019.00038
复制
发表时间：
2019
期刊：
影响因子：
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通讯作者：
R. Tessier
中科院分区：
文献类型：
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作者：
George Provelengios;Daniel E. Holcomb;R. Tessier
包含来自多个用户的电路的多租户FPGA正在成为云和嵌入式计算环境中的新使用模型。FPGA中不受信任的租户应用程序之间的交互可能会导致新的安全暴露以及侧信道攻击或故障注入的风险。在这项工作中，我们调查的能力，积极的功耗的一个应用程序，以干扰电源网络的程度，导致延迟故障在同一FPGA上的第二个应用程序。特别是，我们确定的机制，电源电压受到干扰的攻击，我们的特征作为一个函数的时间，攻击者消耗的功率，和受害者相对于攻击者的位置的干扰的大小。我们强调可用于减轻攻击的策略，包括低成本的监控电路，可以识别攻击的来源，使攻击者的FPGA的使用可以被撤销。
Multi-tenant FPGAs that contain circuits from multiple users are emerging as a new usage model in cloud and embedded computing environments. Interactions between untrusting tenant applications in an FPGA can enable new security exposures and the risk of side channel attacks or fault injection. In this work, we investigate the ability for aggressive power consumption of one application to disturb the power network to an extent that causes delay faults in a second application on the same FPGA. In particular, we identify the mechanisms by which the supply voltage is disturbed by the attack, and we characterize the magnitude of the disturbance as a function of time, power consumed by attacker, and position of the victim relative to the attacker. We highlight strategies that can be used to mitigate attacks, including low-cost monitoring circuits that can identify the source of an attack so that the attacker's use of the FPGA can be revoked.