Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization
Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization
复制标题
用于采样保持电路的低压 CMOS 模拟自举开关：设计和芯片表征
DOI：
10.1109/iscas.2005.1465058
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
M. Sawan
中科院分区：
文献类型：
--
作者：
C. Fayomi;G. Roberts;M. Sawan
本文介绍了基于自举低压模拟 CMOS 开关的新颖实现的采样保持电路的设计和表征。该电路的核心是新型低电压、低应力 CMOS 时钟倍压器。通过使用虚拟开关，自举开关引起的电荷注入大大减少，从而提高了采样保持精度。 0.18/spl mu/m数字CMOS工艺的实验结果表明，在1.0 V电源电压下可以获得大于10位的分辨率。电路也可以在接近晶体管阈值（例如 0.65V）的电源电压下运行。
This paper presents the design and characterization of a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced, resulting in improved sample-and-hold accuracy. Experimental results in a 0.18 /spl mu/m digital CMOS process show that a resolution greater than 10 bits can be obtained with a 1.0 V supply voltage. Circuit operation is also possible for supply voltages close to the transistor threshold (e.g., 0.65 V).