Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
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Clifford Gate 优化和 T Gate 调度：使用拓扑组件的排队模型
DOI：
10.1109/nanoarch47378.2019.181305
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Robert Basmadjian
中科院分区：
文献类型：
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作者：
A. Paler;Robert Basmadjian
Clifford门在Clifford+T电路的优化中起着重要作用。减少Clifford门的数量和深度，以及T门的最佳调度，会影响执行量子电路的硬件和时间成本。本文主要研究表面量子纠错码保护电路。为表面代码编译量子电路的结果被称为拓扑组装。我们使用排队论建模的编译程序集的一部分，评估模型，并作出经验观察，至少对于某些Clifford+T电路（例如加法器），该程序集的执行时间不会增加时，可用的硬件是有限的。这是一个有趣的属性，因为它表明T门调度和Clifford门优化有可能节省硬件和执行时间。
Clifford gates play a role in the optimisation of Clifford+T circuits. Reducing the count and the depth of Clifford gates, as well as the optimal scheduling of T gates, influence the hardware and the time costs of executing quantum circuits. This work focuses on circuits protected by the surface quantum error-correcting code. The result of compiling a quantum circuit for the surface code is called a topological assembly. We use queuing theory to model a part of the compiled assemblies, evaluate the models, and make the empiric observation that at least for certain Clifford+T circuits (e.g. adders), the assembly’s execution time does not increase when the available hardware is restricted. This is an interesting property, because it shows that T gate scheduling and Clifford gate optimisation have the potential to save both hardware and execution time.
DOI：
10.1109/micro.2018.00072
发表时间：
2018-09
期刊：
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
影响因子：
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作者：
Yongshan Ding;Adam Holmes;Ali JavadiAbhari;D. Franklin;M. Martonosi;F. Chong
通讯作者：
Yongshan Ding;Adam Holmes;Ali JavadiAbhari;D. Franklin;M. Martonosi;F. Chong