Post-silicon debug using programmable logic cores
Post-silicon debug using programmable logic cores
复制标题
使用可编程逻辑内核进行硅后调试
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
S. Wilton
中科院分区：
文献类型：
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作者：
Bradley R. Quinton;S. Wilton
制造功能正确的集成电路正变得越来越困难。无论设计者多么细心，总会有集成电路被制造出来，但并不像预期的那样运行。提供一种有效调试这些集成电路的方法对于帮助定位问题和减少创建功能正常的芯片所需的重新旋转次数至关重要。在本文中，我们证明了可编程逻辑核(PLC)和灵活的网络可以提供这种调试能力。我们给出了一个体系结构和示例实现。我们表明，对于许多目标IC来说，这种建议的体系结构的面积开销将远低于10%。
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabricated, but do not operate as expected. Providing a means to effectively debug these integrated circuits is vital to help pin-point problems and reduce the number of re-spins required to create a correctly-functioning chip. In this paper, we show that programmable logic cores (PLCs) and flexible networks can provide this debugging capability. We present an architecture and example implementation. We show that the area overhead of this proposed architecture would be well below 10% for many target ICs.