DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies
DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies
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DPPM 减少方法和新的缺陷导向测试方法应用于先进 FinFET 技术
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
J. Rajski
中科院分区：
文献类型：
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作者：
Will Howell;F. Hapke;Edward Brazil;S. Venkataraman;R. Datta;Andreas Glowatz;W. Redemund;J. Schmerberg;A. Fast;J. Rajski
本文介绍了采用先进的FinFET技术制造的设计中应用的新的缺陷导向测试（DOT）方法/模式所实现的DPPM降低结果。本文重点研究了针对FinFET晶体管小延迟缺陷的时序感知单元感知测试（TA-CAT）模式，以及一种明确针对芯片布局相关单元邻域缺陷的新的DOT方法。本文将介绍应用于FinFET技术设计的传统卡点/过渡模式、传统CAT模式、TA-CAT模式以及细胞邻近模式的测试结果。此外，还将讨论与系统级测试失败的关系。
This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.