Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
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用于减少路径计数和路径延迟故障可测试性的组合电路的重新综合
DOI：
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发表时间：
1996
期刊：
影响因子：
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通讯作者：
K. Cheng
中科院分区：
文献类型：
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作者：
Angela Krstic;K. Cheng
路径延迟故障模型最适合检测可能导致延迟故障的分布式制造缺陷。然而，现代设计中的路径数量可能非常大，并且许多实际设计的路径延迟可测试性很低。本文介绍了如何对组合电路进行再综合，以减少电路中的总路径数。我们的结果表明，在不增加电路中最长敏感路径的面积和/或延迟的情况下，可以获得显著减少路径数量的电路。对路径延迟测试的研究表明，在许多电路中，很大一部分路径没有能够保证检测到延迟故障的测试。如果这样的路径数目减少，则电路的路径延迟可测试性将增加。我们表明，在电路中增加少量的测试点可以帮助减少给定设计中的这类路径的数量。
Path delay fault model is the most suitable model for detectingdistributed manufacturing defects which can cause delayfaults. However, the number of paths in a modern design can beextremely large and the path delay testability of many practicaldesigns is very low. In this paper we show how to resynthesize acombinational circuit in order to reduce the total number of paths inthe circuit. Our results show that it is possible to obtain circuitswith a significant reduction in the number of paths while notincreasing area and/or delay of the longest sensitizable path in thecircuit.Research on path delay testing shows that in many circuits a largeportion of paths does not have a test that can guarantee detection ofa delay fault. The path delay testability of a circuit would increaseif the number of such paths is reduced. We show that addition of asmall number of test points into the circuit can help reducing thenumber of such paths in the given design.