TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages
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DOI：
10.1109/tvlsi.2019.2935227
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发表时间：
2019-04
影响因子：
2.8
通讯作者：
Shan Shen;Tianxiang Shao;Xiaojing Shang;Yichen Guo;Ming Ling;Jun Yang;Longxing Shi
中科院分区：
文献类型：
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作者：
Shan Shen;Tianxiang Shao;Xiaojing Shang;Yichen Guo;Ming Ling;Jun Yang;Longxing Shi
为了缓解日益严重的“功率墙”问题，越来越多的应用需要将其工作电压扩展到包括近阈值区域在内的宽电压范围。然而，由于过程波动，近阈值电压下静态随机存取存储器（SRAM）单元的读延迟分布表现出比标称电压下更严重的长尾特征。这种SRAM延迟的退化使得基于SRAM的缓存也成为系统的性能瓶颈。为了避免不可靠的数据读取，电路级研究通过牺牲芯片面积和缓存阵列的静态功率，在位单元中使用更大/更多的晶体管。体系结构研究提出在容错缓存中采用辅助纠错或块禁用/重映射方法，由于访问逻辑复杂，导致命中延迟和能量效率恶化。本文提出了一种时序推测（TS）缓存，以提高缓存频率并提高低电源电压下的能源效率。在TS高速缓存中，位线（BLs）的电压差由一个感测放大器（SA）连续评估两次，并且可以比以前的方法更早地检测到访问时序误差。根据成品芯片的测量结果，在0.5 v和0.6 v电源电压下，与传统方案相比，TS L1高速缓存的频率分别大幅提高到1.62倍和1.92倍。
To mitigate the ever-worsening “power wall” problem, more and more applications need to expand their working voltage to the wide-voltage range including the near-threshold region. However, the read delay distribution of the static random access memory (SRAM) cells under the near-threshold voltage shows a more serious long-tail characteristic than that under the nominal voltage due to the process fluctuation. Such degradation of SRAM delay makes the SRAM-based cache a performance bottleneck of systems as well. To avoid unreliable data reading, circuit-level studies use larger/more transistors in a bitcell by sacrificing chip area and the static power of cache arrays. Architectural studies propose the auxiliary error correction or block disabling/remapping methods in fault-tolerant caches, which worsen both the hit latency and energy efficiency due to the complex accessing logic. This article proposes a timing-speculation (TS) cache to boost the cache frequency and improve energy efficiency under low supply voltages. In the TS cache, the voltage differences of bitlines (BLs) are continuously evaluated twice by a sense amplifier (SA), and the access timing error can be detected much earlier than that in prior methods. According to the measurement results from the fabricated chips, the TS L1 cache aggressively increases its frequency to $1.62\times $ and $1.92\times $ compared with the conventional scheme at 0.5- and 0.6-V supply voltages, respectively.