Design error diagnosis and correction via test vector simulation
Design error diagnosis and correction via test vector simulation
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DOI：
10.1109/43.811329
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发表时间：
1999-12
期刊：
影响因子：
--
通讯作者：
A. Veneris;I. Hajj
中科院分区：
文献类型：
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作者：
A. Veneris;I. Hajj
随着数字VLSI电路设计复杂性的增加，在合成过程中会出现逻辑设计误差。本文提出了一种基于测试向量仿真的多设计错误诊断与修正方法。通过隐式枚举错误行来执行诊断，以避免随着错误数量的增加而导致错误空间的指数爆炸。修正过程中的再合成尽可能少，以便保留设计中投入的大部分工程努力。由于这两个步骤都是基于测试向量模拟，因此该方法适用于没有全局二值决策图表示的电路。在ISCAS’85基准电路上的实验证明了该方法的鲁棒性和误差分辨率。实验还表明，测试矢量仿真确实是一种有吸引力的技术，可用于数字VLSI电路的多重设计错误诊断和校正。
With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.