A Model for Multilevel Phase-Change Memories Incorporating Resistance Drift Effects
A Model for Multilevel Phase-Change Memories Incorporating Resistance Drift Effects
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DOI：
10.1109/jeds.2014.2357577
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发表时间：
2015
影响因子：
2.3
通讯作者：
R. A. Cobley;C. Wright;J. V. Vázquez Diosdado
中科院分区：
文献类型：
--
作者：
R. A. Cobley;C. Wright;J. V. Vázquez Diosdado
相变存储器作为未来非易失性固态电存储的最有前途的技术而出现。然而，为了在主流存储应用中有效地竞争，多级单元能力是最期望的。不幸的是，相变存储器表现出编程电阻（和阈值切换电压）的时间漂移，这似乎是非晶或部分非晶相的基本和普遍性质。因此，相变器件模型应该以现实的方式包括这些漂移效应，以便电路和系统设计人员可以评估多级相变存储器在各种潜在应用中的可能性能。因此，在本文中，我们提出了一个全面的SPICE为基础的模型相变器件，包括编程到多个电阻水平的能力，预测的漂移的单元电阻（和阈值电压）随时间的推移，和建模的随机性固有的电阻漂移现象的能力。使用该模型的多级编程和漂移现象的模拟和实验结果相比，有很好的协议。
Phase change memories are emerging as a most promising technology for future nonvolatile, solid-state, electrical storage. However, to compete effectively in mainstream storage applications, a multilevel cell capability is most desirable. Unfortunately, phase-change memories exhibit a temporal drift in programmed resistance (and in threshold switching voltage) which appears to be a fundamental and universal property of the amorphous or partially amorphous phase. Phase-change device models should therefore include these drift effects in a realistic way so that circuit and systems designers can assess the likely performance of multilevel phase-change memories in a variety of potential applications. In this paper, therefore, we present a comprehensive SPICE-based model for phase-change devices that includes the capability for programming into multiple resistance levels, the prediction of the drift of cell resistance (and threshold voltage) with time, and the capability for modeling the randomness inherent to the resistance drift phenomenon. Simulations of multilevel programming and drift phenomena using the model are presented and compared to experimental results, with which there is very good agreement.