Ultra-low power probabilistic IMT neurons for stochastic sampling machines
Ultra-low power probabilistic IMT neurons for stochastic sampling machines
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用于随机采样机的超低功耗概率 IMT 神经元
DOI：
10.23919/vlsit.2017.7998148
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
S. Datta
中科院分区：
文献类型：
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作者：
M. Jerry;A. Parihar;B. Grisafe;A. Raychowdhury;S. Datta
随机采样机（SSM）利用来自概率尖峰神经元的神经采样来逃避局部最小值并防止训练数据集的过拟合[1]。与确定性实现相比，这能够改善错误率，并且进而能够实现更低的位精度、减小的芯片面积和降低的能耗。在这项工作中，我们的实验证明：（i）绝缘体到金属相变（IMT）神经元具有创纪录的低峰值工作功率为11.9μW的VDD=0.7V：（ii）二氧化钒（VO 2）中的IMT为实现用于SSM的紧凑随机IMT神经元提供了自然的概率硬件基板;（iii）使用实验校准的设备建模在MNIST数据库[2]上实现用于模式识别的SSM。将这些结果与22 nm CMOS ASIC进行比较，其显示基于随机IMT神经元的SSM导致系统功耗降低4.5倍。
Stochastic sampling machines (SSM) utilize neural sampling from probabilistic spiking neurons to escape local minima and prevent overfitting of training datasets [1]. This enables improved error rates compared to deterministic implementations, and, in turn, enables lower bit precision, decreased chip area, and reduced energy consumption. In this work, we experimentally demonstrate: (i) Insulator-to-Metal Phase Transition (IMT) neurons with record low peak operating power of 11.9μW at VDD=0.7V; (ii) the IMT in vanadium dioxide (VO2) provides a natural probabilistic hardware substrate for realizing a compact stochastic IMT neuron for SSMs; (iii) implementation of SSM for pattern recognition on MNIST database [2] using experimentally calibrated device modeling. These results are compared to a 22nm CMOS ASIC which shows stochastic IMT neuron based SSMs result in a 4.5x reduction in system power consumption.