Process variability at the 65nm node and beyond
Process variability at the 65nm node and beyond
复制标题
65 纳米及以上节点的工艺可变性
DOI：
10.1109/cicc.2008.4672005
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
S. Nassif
中科院分区：
文献类型：
--
作者：
S. Nassif
制造引起的变化的影响已被公认为现代集成电路设计的一阶障碍[1]。目前正在进行许多研究工作，以（a）理解和表征可变性[2]，（B）预测其对电路行为的影响[3]，以及（c）开发布局和电路设计技术以减少可变性的影响[4]。同时，除了最先进的高性能设计，迁移到65纳米以下技术节点的成本不断增加，正在减缓先进技术的采用。这种放缓使当前的努力能够赶上并帮助减轻作为障碍的可变性。
The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design [1]. Numerous research efforts are currently underway to (a) understand and characterize variability[2], to (b) predict its impact on circuit behavior[3], and (c) to develop layout and circuit design techniques to reduce the impact of variability[4]. Simultaneously, except for the most advanced high performance designs, the increasing cost of migrating to sub-65 nm technology nodes is slowing down adoption of advanced technologies. This slow down is allowing current efforts to catch up and help mitigate variability as an impediment.