Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing
复制标题
并行异步图像处理骨架化算法的硬件实现
DOI：
10.1007/s11265-008-0283-6
复制
发表时间：
2009
期刊：
影响因子：
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通讯作者：
P. Dudek
中科院分区：
文献类型：
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作者：
A. Lopich;P. Dudek
本文提出了一种FPGA实现的专用蜂窝处理器阵列设计的异步二进制图像的卷积。该算法是基于迭代细化利用“草火”变换方法。本工作的目的是测试一个完全并行的异步处理器阵列的性能，并评估波传播速度的不均匀性。一个概念验证设计已经实施和评估，结果和讨论。
This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on iterative thinning utilizing a ‘grassfire’ transformation approach. The purpose of this work was to test the performance of a fully parallel asynchronous processor array and to evaluate the inhomogeneity of wave propagation velocity. A proof-of-concept design has been implemented and evaluated, the results are presented and discussed.