Development of SOI pixel process technology
Development of SOI pixel process technology
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DOI：
10.1016/j.nima.2010.04.081
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发表时间：
2011-04-21
影响因子：
1.4
通讯作者：
Motoyoshi, M.
中科院分区：
文献类型：
--
作者：
Arai, Y.;Miyoshi, T.;Motoyoshi, M.
开发了一种用于像素化辐射探测器的绝缘体上硅（SOI）工艺。它是基于0.2 μ M CMOS全耗尽（FD-）SOI技术。SOI晶片由用于感测部分的厚的高电阻率衬底和用于CMOS电路的薄Si层组成。两种类型的像素探测器，一个集成型和其他计数型，开发和测试。为了进一步提高探测器的性能，我们引入了一种新的工艺技术--掩埋p阱（BPW）技术来抑制背栅效应。我们还在开发垂直（3D）集成技术，以实现更高的密度。(C)2010 Elsevier B. V.保留所有权利。
A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 mu M CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors.For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density. (C) 2010 Elsevier B.V. All rights reserved.