Effect of switch resistance on the SC integrator settling time

Effect of switch resistance on the SC integrator settling time
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DOI:
10.1109/82.769789
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发表时间:
1999-06
期刊:
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing
影响因子:
--
通讯作者:
U. Chilakapari;T. Fiez
U. Chilakapari;T. Fiez
中科院分区:
其他
文献类型:
--
作者:
U. Chilakapari;T. Fiez

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利用一般反馈理论,建立了开关电容积分器的数学模型。该模型用于分析采样和反馈开关电阻对积分器建立时间的影响。如果对应于采样时间常数的频率小于放大器第二极点频率的五倍,则积分器建立时间将降低。对于高达50 k/spl Ω/的开关电阻,反馈开关电阻对积分器建立时间几乎没有影响。
Using general feedback theory, a model is developed for the switched-capacitor integrator. This model is then used to analyze the effects of sampling and feedback switch resistances on the integrator settling time. If the frequency corresponding to the sampling time constant is less than five times the frequency of the second pole of the amplifier, the integrator settling time will be degraded. The feedback switch resistance has little effect on the integrator settling time for switch resistances up to 50 k/spl Omega/.