Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
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集成电路和系统设计。
DOI：
10.1007/978-3-642-17752-1_11
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
Baz A
中科院分区：
文献类型：
--
作者：
Baz A
便携式数字系统不仅需要低功耗，而且需要高效节能，因为它们由低功耗电池或能量收集器供电。随着时间的推移，能量收集系统往往会提供不确定的能量，而不是稳定的能量。现有的存储系统使用延迟元件来应对不同vdd下的问题。然而，这会带来巨大的性能损失，因为延迟元素需要在最坏的环境下遵循最坏情况的时序假设。在本文中，研究了使用典型延迟元件的存储单元和相应控制器之间的延迟不匹配，并发现不同的Vdd值是高度可变的。然后开发了一种速度无关（SI） SRAM存储器，可以帮助避免这种不匹配问题。它也可以用来代替典型的延迟线，用于捆绑数据存储库。在此基础上实现了一个1kb的SI存储库，并从延迟和功耗方面进行了分析。此外，还实现了一个使用SI SRAM作为延迟捆绑器件的1kb捆绑数据存储库。比较研究表明了这些方法的优缺点。
Portable digital systems need to be not just low power but power efficient as they are powered by low batteries or energy harvesters. Energy harvesting systems tend to provide nondeterministic, rather than stable, power over time. Existing memory systems use delay elements to cope with the problems under different Vdds. However, this introduces huge penalties on performance, as the delay elements need to follow the worst case timing assumption under the worst environment. In this paper, the latency mismatch between memory cells and the corresponding controller using typical delay elements is investigated and found to be highly variable for different Vdd values. A Speed Independent (SI) SRAM memory is then developed which can help avoid such mismatch problems. It can also be used to replace typical delay lines for use in bundled-data memory banks. A 1 Kb SI memory bank is implemented based on this method and analysed in terms of the latency and power consumption. In addition, a 1 Kb bundled-data memory bank using SI SRAM as delay bundling devices is also implemented. Comparative studies demonstrate the advantages and disadvantages of these methods.