Substrate noise modeling in early floorplanning of MS-SOCs
Substrate noise modeling in early floorplanning of MS-SOCs
复制标题
MS-SOC 早期布局规划中的基板噪声建模
DOI：
10.1145/1120725.1121025
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
Jin S. Zhang
中科院分区：
文献类型：
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作者：
G. Blakiewicz;M. Jeske;M. Chrzanowska;Jin S. Zhang
针对混合信号片上系统(MS-SOCs)的早期设计规划，提出了模拟块的频率相关灵敏度模型和数字块的噪声注入模型。我们假设没有关于IP核的精确布局信息可用。对于混合信号电路中首选的轻掺杂衬底，我们还提出了大面积噪声端口和小面积敏感端口之间分离依赖耦合的经验公式。我们的FloorPlanner融入了数字和模拟模块之间的交互，从而减少了总体噪声和违反噪声限制的模拟模块的数量。基于MNC布局基准生成的实例的实验结果是非常令人鼓舞的。
We propose a frequency-dependent sensitivity model for analog blocks and a noise injection model for digital blocks in application to early design planning of mixed-signal system-on-chips (MS-SOCs). We assume no precise layout information about IP cores is available. We also propose an empirical formula for separation-dependent coupling between large-area noisy ports and small-area sensitive ports for lightly-doped substrates that are preferred for mixed-signal circuits. The interaction between digital and analog blocks is incorporated into our floorplanner, which reduces the overall noise and the number of analog blocks with noise limit violations. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging.