Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM
Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM
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DOI：
10.1145/3060403.3060423
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发表时间：
2017-05
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影响因子：
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通讯作者：
Chaobing Zhou;Libo Huang;Zhisheng Li;Tan Zhang;Q. Dou
中科院分区：
文献类型：
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作者：
Chaobing Zhou;Libo Huang;Zhisheng Li;Tan Zhang;Q. Dou
在嵌入式处理器中，与桌面或服务器处理器相比，分支预测器所需的RAM资源还远未达到。如何利用有限的资源设计出性能优良的上级分支预测器已成为迫切的挑战。在本文中，我们利用超小型RAM处理器中实现的复杂TAGE的性能。我们首先定义了设计空间探索问题的TAGE在给定的RAM大小和最大全局历史寄存器长度的约束下。然后，在轨迹驱动仿真的基础上，采用改进的粒子群优化算法对具体参数进行高效探索，在RAM为0.125 ~ 4KB的情况下，获得预测精度较高的设计参数。我们发现，对于本文的轨迹，我们的算法探索的1.5KB RAM下的参数可以达到足够的精度。如果我们将RAM资源从8 KB减少到1.5KB，则性能损失相当小。此外，1.5KB TAGE的误预测率比1.5KB Bi-mode降低了63.41%。并且，0.25KB TAGE与4KB GShare具有几乎相同的准确性。
In embedded processors, the RAM resources required by branch predictor compared to desktop or server processors are far from being reached. Utilizing the limited resources to design superior performance branch predictor has become urgent challenge. In this paper, we exploit the performance of complex TAGE implemented in ultra-small RAM processor. We first define design space exploration problem of the TAGE under the constraints of given RAM size and maximum global history register length. Then, based on the trace-driven simulation, the improved Particle Swarm Optimization algorithm is used to efficiently explore the specific parameters, rewarding design parameters with high prediction accuracy under RAM ranging from 0.125KB to 4KB. We found that, for the traces of this paper, the parameters under the 1.5KB RAM explored by our algorithm can achieve adequate accuracy. The performance loss is considerably small if we reduce the RAM resources from 8KB to 1.5KB. In addition, the misprediction rate of 1.5KB TAGE are reduced by 63.41% compared to 1.5KB Bi-mode. And, 0.25KB TAGE has almost the same accuracy with 4KB GShare.