ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA
ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA
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DOI：
10.1109/fccm.2018.00011
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发表时间：
2018-04
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影响因子：
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通讯作者：
Zhenyuan Ruan;Tong He;Bojie Li;Peipei Zhou;J. Cong
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作者：
Zhenyuan Ruan;Tong He;Bojie Li;Peipei Zhou;J. Cong
近年来，我们见证了FPGA在许多高性能系统中的出现。这是由于FPGA的高度可重构性和改进的用户友好的编程环境。OpenCL由主要FPGA供应商支持，是一个高级编程平台，将硬件开发人员从复杂且容易出错的HDL开发中解放出来。虽然OpenCL公开了一种类似GPU的编程模型，非常适合计算密集型任务，但在许多部署FPGA的最先进系统中，我们观察到工作负载是流媒体式的，这是通信密集型的。这种不匹配导致低吞吐量和高端到端延迟。在本文中，我们提出了ST-Accel，一个新的高层次的编程平台上的流媒体应用程序的FPGA。它具有以下优点：（i）ST-Accel采用多处理编程模型来捕获流应用固有的流水线级并行性，同时减少端到端延迟。(ii)基于消息传递的主机/FPGA通信模型用于避免共享存储器的一致性问题，从而实现在内核执行期间的主机/FPGA通信。(iii)ST-Accel为I/O设备提供了一个高级别的抽象，以支持直接的I/O设备访问，消除了主机CPU的开销，减少了I/O延迟。(iv)ST-Accel支持解耦的访问/执行架构，以最大限度地提高I/O设备的利用率。(v)重新设计了主机/FPGA通信接口，以满足延迟关键型和吞吐量关键型场景的需求。在Amazon AWS云和本地机器上的实验结果表明，与OpenCL相比，ST-Accel可以实现1.6倍-166倍的吞吐量和1/3的延迟。
In recent years we have witnessed the emergence of the FPGA in many high-performance systems. This is due to FPGA's high reconfigurability and improved user-friendly programming environment. OpenCL, supported by major FPGA vendors, is a high-level programming platform that liberates hardware developers from having to deal with the complex and error-prone HDL development. While OpenCL exposes a GPU-like programming model, which is well-suited for compute-intensive tasks, in many state-of-art systems that deploy FPGA, we observe that the workloads are streaming-like, which is communication-intensive. This mismatch leads to low throughput and high end-to-end latency. In this paper, we propose ST-Accel, a new high-level programming platform for streaming applications on FPGA. It has the following advantages: (i) ST-Accel adopts the multiprocessing programming model to capture the inherent pipeline-level parallelism of streaming applications while reducing the end-to-end latency. (ii) A message-passing-based host/FPGA communication model is used to avoid the coherency issue of shared memory, thus enabling host/FPGA communication during kernel execution. (iii) ST-Accel provides a high-level abstraction for I/O devices to support direct I/O device access that eliminates the overhead of host CPU and reduces the I/O latency. (iv) ST-Accel enables the decoupled access/execute architecture to maximize the utilization of I/O devices. (v) The host/FPGA communication interface is redesigned to cater to the demands of both latency-critical and throughput-critical scenarios. The experimental results on the Amazon AWS cloud and local machine show that ST-Accel can achieve 1.6X-166X throughput and 1/3 latency for typical streaming workloads when compared to OpenCL.