2.5D and 3D technology challenges and test vehicle demonstrations
2.5D and 3D technology challenges and test vehicle demonstrations
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DOI：
10.1109/ectc.2012.6248968
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发表时间：
2012-07
期刊：
影响因子：
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通讯作者：
J. Knickerbocker;P. Andry;E. Colgan;B. Dang;T. Dickson;X. Gu;C. Haymes;C. Jahnes;Y. Liu;J. Maria;R. Polastre;C. Tsang;L. Turlapati;B. Webb;L. Wiggins;S. Wright
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文献类型：
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作者：
J. Knickerbocker;P. Andry;E. Colgan;B. Dang;T. Dickson;X. Gu;C. Haymes;C. Jahnes;Y. Liu;J. Maria;R. Polastre;C. Tsang;L. Turlapati;B. Webb;L. Wiggins;S. Wright
三维(3D)芯片与直通硅通孔(TSV)的集成可以利用2.5D硅封装和3D芯片堆栈等微体系结构设计实现增强性能、功率效率和降低成本的系统优势。集成在模块中的2.5D硅封装和3D芯片堆栈结构各自具有独特的技术挑战，但与传统封装解决方案相比，每种结构都可以提供更低的延迟和更高的带宽等系统优势。使用2.5D或3D集成的其他系统优势可以包括产品小型化或在相同尺寸的产品中增加功能。3D技术利用系统应用的适当设计和微体系结构，可以帮助芯片制造，以降低成本，实现子组件的异构性集成，模块化设计和子组件设计重用，从而降低开发成本和缩短上市时间。2.5D和3D技术可以缩短电路之间的互连长度，从而实现更低的功耗和更低的延迟，并增加互连的数量，从而支持比传统的2D片外互连更高的带宽。适当的设计基本规则、时钟和电气模型应与TSV和硅到硅互连电气参数等定义良好的技术属性相匹配。此外，对于已知良好的芯片(KGD)的晶片测试方法和高成品率组装集成方法对于获得集成的2.5D和3D模块非常重要。对于复杂的3D集成，适当考虑使用TSV和硅到硅互连堆叠的模块或集成芯片可能需要冗余和整体修复方法。2.5D和3D技术挑战可能包括增加功率传输和冷却要求，以满足这些结构增加的电路密度和功率密度。对于小型、低功耗应用，如移动设备，2.5D和3D技术可以通过性能优势和节能提供实质性好处，并为相同功能带来更长的电池寿命。对于一些高性能和高功率应用，2.5D方法简化了异种芯片集成，而不需要增加功率密度和散热冷却密度。然而，一些使用3D技术的高性能和高功率应用可能需要广泛的功率输送规划，具有本地化功率调节和专门的冷却方法，以避免芯片堆叠温度过高，同时利用这些异质芯片之间的短链接可以提供的性能收益。使用多核处理器和宽I/O DRAM、EDRAM、SRAM或高速缓存堆栈的3D芯片堆栈可以以更低的延迟提供高带宽、性能改进。除了上述2.5D和3D的功率传输和热挑战外，还存在3D制造和行业兼容性挑战。技术挑战包括与TSV的晶片集成和精加工、已知良好芯片(KGD)的测试、组装和模块集成。基础设施兼容性和使用新发展的行业标准，例如用于晶片处理的半3D标准和用于宽I/O存储器的JEDEC标准，仅举两例。晶片运输的标准正在制定中，随着时间的推移，其他3D兼容性标准也在制定中。这份研究报告描述了使系统能够使用2.5D和3D技术的关键挑战。文中还重点介绍了2.5维和3D硬件演示的进展和结果，并对未来的演示进行了展望。
Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSV's, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.