Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits
Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits
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针对模拟和数字 CMOS 电路的细粒度可重构架构的演化实验
DOI：
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发表时间：
1999
期刊：
影响因子：
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通讯作者：
Wei
中科院分区：
文献类型：
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作者：
A. Stoica;D. Keymeulen;R. Tawel;C. Salazar;Wei
本文介绍了一个细粒度的可编程晶体管阵列（PTA）架构的架构细节，并说明了它的使用在模拟和数字电路的合成进化实验。PTA芯片内置在CMOS中，以允许使用模拟PTA通过进化设计获得的电路立即在硬件中部署和验证，此外，还可以对仅通过模拟（外部进化）进行的进化与芯片在环（内部）进化进行基准测试和比较。介绍了模拟计算电路和逻辑反相器的发展。通过软件进化的合成发现了几种满足先验约束的潜在解决方案，然而，当移植到硬件时，只有一小部分被证明是有效的。直接在硬件中进化的电路在移植到不同的芯片时被证明是稳定的。在任何一种情况下，软件和硬件实验都表明，当灰度（相对于二进制开关）被用来定义电路连接时，进化可以加速。总的来说，只有直接在硬件中进行进化才能保证有效的解决方案。
The paper describes the architectural details of a fine-grained programmable transistor array (PTA) architecture and illustrates its use in evolutionary experiments on the synthesis of both analog and digital circuits. A PTA chip was built in CMOS to allow circuits obtained through evolutionary design using a simulated PTA to be immediately deployed and validated in hardware and, moreover, enables a benchmarking and comparison of evolutions carried out via simulations only (extrinsic evolution) with the chip-in-the-loop (intrinsic) evolutions. The evolution of an analog computational circuit and a logical inverter are presented. Synthesis by software evolution found several potential solutions satisfying the a priori constraints, however, only a fraction of these proved valid when ported to the hardware. The circuits evolved directly in hardware proved stable when ported to different chips. In either case, both software and hardware experiments indicate that evolution can be accelerated when gray-scale (as opposed to binary switches) were used to define circuit connectivity. Overall, only evolution directly in hardware appears to guarantee a valid solution.