ARC: An Automated Approach to Resiliency for Lossy Compressed Data via Error Correcting Codes

ARC: An Automated Approach to Resiliency for Lossy Compressed Data via Error Correcting Codes
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DOI:
10.1145/3431379.3460638
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发表时间:
2021-06
期刊:
Proceedings of the 30th International Symposium on High-Performance Parallel and Distributed Computing
影响因子:
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通讯作者:
Dakota Fulp;Alexandra Poulos;Robert Underwood;Jon C. Calhoun
Dakota Fulp;Alexandra Poulos;Robert Underwood;Jon C. Calhoun
中科院分区:
其他
文献类型:
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作者:
Dakota Fulp;Alexandra Poulos;Robert Underwood;Jon C. Calhoun

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高性能计算(HPC)系统的进步导致了复杂的应用程序,这些应用程序通过创建大量数据来给I/O子系统带来压力。有损压缩可显著减小数据大小,但单个错误会使有损压缩数据不可用。这种敏感性源于压缩数据中每比特的高信息含量,并且是一个关键问题,因为导致比特翻转的软错误在HPC系统中变得越来越普遍。虽然许多工作已经改善了有损压缩机的性能,很少有人试图解决这个关键的弱点。ARC:Automated Resiliency for Compression自动恢复压缩考虑到用户定义的存储、吞吐量和弹性约束,ARC会在编码数据之前自动确定最佳纠错码(ECC)配置。我们进行了广泛的故障注入研究,以充分了解软错误对有损压缩数据的影响,以及如何最好地保护它。我们评估ARC的可扩展性,性能,弹性和易用性。我们发现在一个40核的节点上,编码和解码表现出高达3730 MB/s和3602 MB/s的吞吐量。ARC还检测和纠正多位错误,在存储和吞吐量方面具有可调的开销。最后,我们展示了使用ARC的方便性以及在确定约束条件时如何考虑系统故障率。
Progress in high-performance computing (HPC) systems has led to complex applications that stress the I/O subsystem by creating vast amounts of data. Lossy compression reduces data size considerably, but a single error renders lossy compressed data unusable. This sensitivity stems from the high information content per bit in compressed data and is a critical issue as soft errors that cause bit-flips have become increasingly commonplace in HPC systems. While many works have improved lossy compressor performance, few have sought to address this critical weakness. This paper presents ARC: Automated Resiliency for Compression. Given user-defined constraints on storage, throughput, and resiliency, ARC automatically determines the optimal error-correcting code (ECC) configuration before encoding data. We conduct an extensive fault injection study to fully understand the effects of soft errors on lossy compressed data and how to best protect it. We evaluate ARC's scalability, performance, resiliency, and ease of use. We find on a 40 core node that encoding and decoding demonstrate throughput up to 3730 MB/s and 3602 MB/s. ARC also detects and corrects multi-bit errors with a tunable overhead in terms of storage and throughput. Finally, we display the ease of using ARC and how to consider a systems failure rate when determining the constraints.