Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families
Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families
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DOI：
10.1109/isec46533.2019.8990962
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发表时间：
2019-07
期刊：
影响因子：
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通讯作者：
L. Schindler;R. van Staden;C. Fourie;C. Ayala;J. A. Coetzee;Tomoyuki Tanaka;Ro Saito;N. Yoshikawa
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文献类型：
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作者：
L. Schindler;R. van Staden;C. Fourie;C. Ayala;J. A. Coetzee;Tomoyuki Tanaka;Ro Saito;N. Yoshikawa
在IARPA SuperTools计划下的这项工作中，我们开发了一个具有脚本支持的布局合成工具。用户指定由用户定义的单元高度和单元宽度约束的约瑟夫森结和电感的相对位置。与三维电感提取工具InductEx紧密集成，可自动生成电感，同时满足合理的设计值。基于这些用户输入，该工具可以根据设计规则和层参数来合成用于多种SFQ电路技术的逻辑单元的物理布局。此外，当设计规则改变或库必须重新设计以用于更先进的制造工艺时，它能够直接再生整个单元库。我们描述了我们的合成工具的方法，并显示适用于RSFQ和AQFP逻辑家庭的结果。
In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.