Hybrid Han Carlson Adder Architecture for Reducing Power and Delay
Hybrid Han Carlson Adder Architecture for Reducing Power and Delay
复制标题
用于降低功耗和延迟的混合 Han Carlson 加法器架构
DOI：
--
复制
发表时间：
2016
期刊：
影响因子：
--
通讯作者：
C. Vivek
中科院分区：
文献类型：
--
作者：
K. Kaarthik;C. Vivek
加法器在算术逻辑单元中起着至关重要的作用。它通常用于构建IC芯片。在IC芯片的制造中，加法器的实现可以通过减少门的数量来减少面积。如果门的数量减少，那么功耗也会减少，同时处理速度也会因延迟的减少而增加。在低功耗的VLSI设计过程中，将实现面积减小、功耗降低、延迟减小和速度提高的过程。本文研究并行前缀加法器（PPA）。并行前缀加法器用于加速二进制加法过程。本论文的工作是比较各种并行前缀加法器，以获得一种能在较短时间内以较小的功耗和面积获得输出的加法器。对它们的输出进行了仿真，并给出了一个比较表，证明了优选加法器可以获得更好的结果。
: Adder plays a vital role in Arithmetic Logic Unit. It is commonly employed in building of an IC chip. In the manufacturing of IC chip the Implementation of Adder is used to Reduce the Area by reducing the Number of gates. If the number of gates gets reduced then Power Consumption is also gets reduced simultaneously the processing speed will be Increased by reduction in Delay. These process of decreased Area, Power Consumption, Delay and Increased Speed will be obtained in Low Power VLSI Design process. In this Paper we consider the Parallel Prefix Adder (PPA). The Parallel Prefix Adders are used to Speed up the Binary Addition Process. The work involves the comparison of various parallel prefix adder to obtain a Adder which can able to obtain the Output in short span of time with consumption of less Power and Area. Their outputs are simulated and a Comparison table have been provided to Justify that the Preferred adder can obtain better Result.