Automatic synthesis of asynchronous circuits from synchronous RTL descriptions
Automatic synthesis of asynchronous circuits from synchronous RTL descriptions
复制标题
根据同步 RTL 描述自动合成异步电路
DOI：
10.1109/norchp.2005.1597024
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
P. Ellervee
中科院分区：
文献类型：
--
作者：
Johnny Öberg;J. Plosila;P. Ellervee
随着ASIC的尺寸缩小到纳米级，工艺参数的可变性将增加。这种可变性使得在整个芯片上分配同步时钟变得非常困难。另一种选择是用具有相同功能的异步部件替换关键的同步部件。主要的问题是，第一，没有建立的工具流程，使设计人员很容易设计一个异步电路，第二，没有建立的设计自动化工具，除了一些实验性的。此外，今天的大多数设计人员都接受过设计同步电路的培训，必须重新培训。在本文中，我们提出了一种解决所有这三个问题的方法，即，它允许设计者从同步域开始，然后自动将电路的同步表示转换为异步表示。
As the dimensions of ASICs shrink down to the nanometer regime, the variability of the process parameters will increase. This variability threatens to make it extremely difficult to distribute a synchronous clock all over the chip. Another option would be to replace critical synchronous parts with asynchronous counterparts with the same functionality. The main problems are, first, there is no established tool-flow that makes it easy for a designer to design an asynchronous circuits, and, second, there are no established design automation tools, except a few experimental ones. In addition, most designers today are trained to design synchronous circuits and have to be retrained. In this paper, we present a method that solves all three of these problems, i.e., it allows a designer to start in the synchronous domain, and then automatically transform the synchronous representation of the circuit into an asynchronous one.