5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager
5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager
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5.7 A 256×256 40nm/90nm CMOS 3D 堆叠 120dB 动态范围可重配置时间分辨 SPAD 成像仪
DOI：
10.1109/isscc.2019.8662355
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
J. Leach
中科院分区：
文献类型：
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作者：
R. Henderson;N. Johnston;S. W. Hutchings;I. Gyongy;T. Abbas;N. Dutton;Max Tyler;Susan Chan;J. Leach
光探测和测距（LIDAR）应用对光学飞行时间（ToF）接收器的动态范围（DR）要求极具挑战性，因为激光回波在2-3年的距离内受到平方反比定律的影响，目标反射率不同，太阳背景[1]高。集成的CMOS spad具有超过140dB的原生DR，通常从几cps的本底噪声扩展到100 Mcps的峰值速率。为了将DR传输到下游DSP，大型SPAD时间分辨率成像阵列必须对每秒数十亿个单光子事件进行计数和计时，这需要大规模并行片上像素处理，以实现实际的I/O功耗和数据速率。混合Cu-Cu键合为实现这些传感器提供了一个大规模生产的平台，通过将高填充因子spad堆叠在密集的纳米级数字处理器[2]上，为近红外优化。目前正在研究涉及像素级直方图、片上峰值检测和TDC/处理器资源共享的堆叠传感器架构[3-5]。
Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100’s Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3–5].