Analysing trade-offs in scan power and test data compression for system-on-a-chip
Analysing trade-offs in scan power and test data compression for system-on-a-chip
复制标题
分析片上系统的扫描功率和测试数据压缩之间的权衡
DOI：
10.1049/ip-cdt:20020450
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
N. Nicolici
中科院分区：
文献类型：
--
作者：
P. Rosinger;P. T. Gonciari;B. Al;N. Nicolici
研究了扫描测试过程中测试数据压缩与功耗的关系。使用ISCAS89基准电路的权衡分析表明，通过采用最近提出的对称编码方案并改变W-SLR算法中的加权参数，嵌入式核设计者可以显式地控制扫描功率和测试数据量。
This paper investigates the relationship between test data compression and power dissipation during scan testing. Trade-off analysis using ISCAS89 benchmark circuits show that by employing the recently proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can explicitly control the scan power and volume of test data.