Experimental investigation of buffer traps physical mechanisms on the gate charge of GaN-on-Si devices under various substrate biases
Experimental investigation of buffer traps physical mechanisms on the gate charge of GaN-on-Si devices under various substrate biases
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DOI：
10.1063/1.5124871
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发表时间：
2020-02-24
影响因子：
4
通讯作者：
Yuan, Jiann-Shiun
中科院分区：
文献类型：
--
作者：
Yang, Wen;Yuan, Jiann-Shiun
研究了不同衬底偏压下GaN-on-Si功率器件的栅电荷变化（Δ Q（g））。在晶圆上的脉冲模式电压应力测量检查，以探讨不同的陷阱机制的物理洞察到Q（g）的特性。不同的注入电子与缓冲陷阱相互作用导致Q（g）在负（正）衬底偏压下显着降低（增加）。在负衬底偏压和正衬底偏压下的应力之后，Δ Q（gd）到Δ Q（gs）的不同程度的退化表明GaN缓冲层中类受主陷阱的不均匀分布和类施主陷阱的均匀分布。利用与Δ Q（g）位移相关联的Arrhenius图，提取了三个主要的缓冲陷阱，其激活能分别为E-V + 0.542eV、E-C-0.604eV和E-C-0.608eV。
The gate charge change (Delta Q(g)) of GaN-on-Si power devices subjected to different substrate biases has been investigated. On-wafer pulse-mode voltage stress measurement is examined to probe the physical insight of different trap mechanisms into Q(g) characteristics. Distinct injected electrons interacting with the buffer traps lead to a significant decrease (increase) in Q(g) under negative (positive) substrate bias. Different levels of degradation on Delta Q(gd) to Delta Q(gs) after stress under negative and positive substrate biases indicate uneven distribution of acceptor-like traps and uniform distribution of donor-like traps in the GaN buffer level. Using Arrhenius plots associated with the Delta Q(g) shift, three dominant buffer traps with activation energies of E-V + 0.542eV, E-C -0.604eV, and E-C -0.608eV are extracted.