Write mode aware loop tiling for high performance low power volatile PCM
Write mode aware loop tiling for high performance low power volatile PCM
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DOI：
10.1145/2593069.2593244
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发表时间：
2014-06
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通讯作者：
Keni Qiu;Qing'an Li;C. Xue
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作者：
Keni Qiu;Qing'an Li;C. Xue
构建PCM，特别是MLC PCM作为MCU的主存储器是一种很有前途的替代传统DRAM部署的技术。然而，PCM/MLC PCM存在写入延迟长和写入能量大的问题。最近的工作提出了一种编译器指导的双写(CDDW)方案，通过对不同的写操作采用快写或慢写模式来克服PCM的缺点。我们观察到写实例的生命周期很长，对于大规模循环，只能通过昂贵的慢模式写入。提出了一种写模式感知的循环分片方法，有效地缩短了写实例的生命周期，最大限度地增加了循环中高效的快速写入次数。实验结果表明，与CDDW方法相比，该方法在一组基准测试中平均提高了50.8%的性能，减少了32.0%的动态能量。
Architecting PCM, especially MLC PCM, as main memory for MCUs is a promising technique to replace conventional DRAM deployment. However, PCM/MLC PCM suffers from long write latency and large write energy. Recent work has proposed a compiler directed dual-write (CDDW) scheme to combat the drawbacks of PCM by adopting fast or slow write mode for different write operations. We observe that write instances' lifetime is very long and can only be written by the expensive slow mode for large-scale loops. This paper proposes a write mode aware loop tiling approach to effectively reduce the lifetime of write instances and maximize the number of efficient fast writes in loops. The experimental results show that the proposed approach improves performance by 50.8% and reduces dynamic energy by 32.0% across a set of benchmarks compared to the CDDW approach on average.