An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices
An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices
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DOI：
10.1109/isvlsi51109.2021.00043
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发表时间：
2021-05
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通讯作者：
Mohammed E. Elbtity;Abhishek Singh;Brendan Reidy;Xiaochen Guo;Ramtin Zand
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文献类型：
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作者：
Mohammed E. Elbtity;Abhishek Singh;Brendan Reidy;Xiaochen Guo;Ramtin Zand
在本文中，我们开发了一个在内存中的模拟计算（IMAC）架构实现突触行为和激活功能的非易失性存储器阵列。利用自旋轨道力矩磁阻随机存取存储器（SOT-MRAM）器件来实现S形神经元以及二值化突触。首先，它示出了所提出的IMAC架构可以用来实现一个多层感知器（MLP）分类器实现数量级的性能改善相比，以前的混合信号和数字实现。其次，提出了一种异构混合信号和混合精度的CPU-IMAC架构，用于移动的处理器上的卷积神经网络（CNN）推理，其中IMAC被设计为一个协处理器来实现全连接（FC）层，而卷积层在CPU中执行。架构级的分析模型被开发来评估CPU-IMAC架构的性能和能耗。仿真结果显示，基于CPU-IMAC的LeNet和VGG CNN模型的实现分别为MNIST和CIFAR-10模式识别任务节省了6.5%和10%的能源。
In this paper, we develop an in-memory analog computing (IMAC) architecture realizing both synaptic behavior and activation functions within non-volatile memory arrays. Spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices are leveraged to realize sigmoidal neurons as well as binarized synapses. First, it is shown the proposed IMAC architecture can be utilized to realize a multilayer perceptron (MLP) classifier achieving orders of magnitude performance improvement compared to previous mixed-signal and digital implementations. Next, a heterogeneous mixed-signal and mixed-precision CPU-IMAC architecture is proposed for convolutional neural networks (CNNs) inference on mobile processors, in which IMAC is designed as a co-processor to realize fully-connected (FC) layers whereas convolution layers are executed in CPU. Architecture-level analytical models are developed to evaluate the performance and energy consumption of the CPU-IMAC architecture. Simulation results exhibit 6.5% and 10% energy savings for CPU-IMAC based realizations of LeNet and VGG CNN models, for MNIST and CIFAR-10 pattern recognition tasks, respectively.