Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory
Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory
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DOI：
10.1109/imw.2013.6582102
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发表时间：
2013-05
期刊：
影响因子：
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通讯作者：
A. Kawasumi;K. Kushida;H. Hara;Y. Unekawa;K. Abe;K. Ikegami;H. Noguchi;E. Kitagawa;C. Kamata;S. Kashiwada;Y. Kato;D. Saida;N. Shimomura;J. Ito;S. Fujita
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文献类型：
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作者：
A. Kawasumi;K. Kushida;H. Hara;Y. Unekawa;K. Abe;K. Ikegami;H. Noguchi;E. Kitagawa;C. Kamata;S. Kashiwada;Y. Kato;D. Saida;N. Shimomura;J. Ito;S. Fujita
提出了用于节能STT MRAM的电路技术，该STT MRAM适合于替代SRAM L2高速缓存存储器。通过消除电压发生器，即使在高于100 MHz的频率下，也可以从掉电模式唤醒，而不会产生任何周期损失。使用自适应脉冲驱动读取电流控制，由发生器消除引起的读取电流变化减轻了50%。交叉耦合的分层开关将不需要的读取电流降低了66%，并提高了读取裕度。
Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin.