Power-Aware Dynamic Cache Partitioning for CMPs
Power-Aware Dynamic Cache Partitioning for CMPs
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DOI：
10.1007/978-3-642-19448-1_8
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发表时间：
2011
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影响因子：
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通讯作者：
Isao Kotera;K. Abe;Ryusuke Egawa;Hiroyuki Takizawa;Hiroaki Kobayashi
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作者：
Isao Kotera;K. Abe;Ryusuke Egawa;Hiroyuki Takizawa;Hiroaki Kobayashi
高速缓存划分和功耗门控技术是实现下一代片上多处理器高性能、低功耗共享高速缓存的重要研究课题。我们提出了一个功耗感知的缓存分区机制，这是一个计划，以实现低功耗和高性能，同时使用功率门控和缓存分区。提出的缓存机制由路径分配功能和功率控制功能组成，每个功能都基于该高速缓存的局部性评估。性能评估结果表明，基于性能的缓存机制在保持性能的前提下，可以降低20%的能耗;基于能量的缓存机制在性能下降13%的情况下，可以降低54%的能耗.硬件实现的结果表明，延迟和面积开销控制所提出的机制是可以忽略不计的，因此几乎不影响整个芯片的设计和性能。
Cache partitioning and power-gating schemes are major research topics to achieve a high-performance and low-power shared cache for next generation chip multiprocessors(CMPs). We propose a poweraware cache partitioning mechanism, which is a scheme to realize both low power and high performance using power-gating and cache partitioning at the same time. The proposed cache mechanism is composed of a way-allocation function and power control function; each function works based on the cache locality assessment. The performance evaluation results show that the proposed cache mechanism with a performanceoriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the mechanism with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%. The hardware implementation results indicate that the delay and area overheads to control the proposed mechanism are negligible, and therefore hardly affect both the entire chip design and performance.