Characterization and Modeling of Mismatch in Cryo-CMOS
Characterization and Modeling of Mismatch in Cryo-CMOS
复制标题
Cryo-CMOS 失配的表征和建模
DOI：
--
复制
发表时间：
2020
影响因子：
2.3
通讯作者：
F. Sebastiano
中科院分区：
文献类型：
--
作者：
P. Hart;M. Babaie;E. Charbon;A. Vladimirescu;F. Sebastiano
本文提出了一种商业40纳米体CMOS工艺在低温下工作的器件匹配研究。晶体管对和线性阵列，优化器件匹配，其特征在于从300 K到4.2 K的温度范围内。与失配相关的器械参数，即，提取阈值电压和电流因子，从其研究作为温度和器件尺寸的函数的绝对值和可变性的变化。结果表明，Pelgrom标度律也是有效的，在4.2 K和简化的Croon模型是能够准确地预测漏极电流失配在整个温度范围内从中等到强反转。此外，线性器件阵列的特性在极低温度下显示出加剧的边缘效应，因此需要在阵列边界处添加虚拟器件。这项研究的结果是第一个模型能够预测在广泛的工作区域和温度的不匹配。
This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.