Hardware implementations of Gaussian elimination over GF(2) for channel decoding algorithms
Hardware implementations of Gaussian elimination over GF(2) for channel decoding algorithms
复制标题
通道解码算法中 GF(2) 的高斯消除的硬件实现
DOI：
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发表时间：
2013
期刊：
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通讯作者：
N. Wehn
中科院分区：
文献类型：
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作者：
S. Scholl;Christopher Stumm;N. Wehn
在本文中，我们调查的硬件实现的高斯消除的二进制矩阵。GF（2）上的高斯消去是几种新的信道解码算法中使用的关键运算，与当前使用的算法相比，它可以大大提高误帧率。我们首先应用国家的最先进的架构，二进制高斯消除解码算法。然后，我们提出了一种新的硬件架构，具有相当少的资源利用率和更高的吞吐量比国家的最先进的解决方案。该设计已在Virtex 7 FPGA上实现并进行了比较。
In this paper, we investigate hardware implementations for Gaussian elimination of binary matrices. Gaussian elimination over GF(2) is a key operation used in several new channel decoding algorithms, that can provide large improvement of frame error rate over currently used algorithms. We first apply state-of-the-art architectures for binary Gaussian elimination to decoding algorithms. Then, we present a new hardware architecture, that has considerably less resource utilization and a higher throughput than state-of-the-art solutions. The designs have been implemented and compared on a Virtex 7 FPGA.